Integrated chips comprise millions of transistor devices. The transistor devices are connected to one another by way of conductive metal interconnects. The metal interconnects have an associated capacitance and resistance, which impacts chip parameters such as signal delay, energy consumption, etc. Therefore, during integrated chip development parasitic extraction of resistive and capacitive (RC) components may be used in conjunction with modeling and timing analysis to describe the performance of an integrated chip.
In prior technology nodes (e.g., 90 nm, 130 nm, etc.), the capacitive and resistive effects of interconnect wires in larger integrated chip designs could be addressed using approximate methods such as pre-characterization of devices and 2.5 D extraction without appreciable loss of accuracy. However, as the size of integrated chip components has decreased RC effects have had an increasing impact on chip parameters. In advanced semiconductor technology nodes (e.g., 22 nm node, 14 nm node, etc.) RC parasitics have a large effect on chip parameters, such that accurate RC parasitic modeling is necessary for proper IC modeling. However, more accurate RC extraction methods (e.g., 3D extraction) are complex and pose a number of limitations for extraction of large-scale designs.